View DS1307ZNTRC02_8638353.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds1307 serial real - time clock (rtc) is a low - power, full binary - coded decimal (bcd) clock/calendar plus 56 bytes of nv sram. address and data are transferred serially through an i 2 c, bidirectional bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 1 2- hour format with am/pm indicator. the ds1307 has a built - in power - sense circuit that detects power failures and automatically switches to the backup supply. timekeeping operation continues while the part operates from the backup supply. typical operating circuit benefits and features ? completely manages all timekeeping functions o real - time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap - year compensation valid up to 2100 o 56 - byte, battery - backed, general - purpose ram with unlimited writes o programmable square - wave output signal ? simple serial port interfaces to most microcontrollers o i 2 c serial interface ? low power operation extends battery backup run time o consumes less than 500na in battery - backup mode with oscillator running o automatic power - fail detect and switch circuitry ? 8- pin dip and 8 - pin so minimizes required space ? optional industrial temperature range: - 40c to +85c supports operation in a wide range of applications ? underwr iters laboratories ? (ul) recognized pin configurations v cc scl sda x1x2 v bat gnd sqw/out v cc scl sda x1x2 v bat gnd sqw/out pdip (300 mils) so (150 mils) top vlew ordering information part temp range voltage (v) pin - package top mark* ds1307+ 0c to +70c 5.0 8 pdip (300 mils) ds1307 ds1307n+ - 40c to +85c 5.0 8 pdip (300 mils) ds 1307n ds1307z+ 0c to +70c 5.0 8 so (150 mils) ds1307 ds1307zn+ - 40c to +85c 5.0 8 so (150 mils) ds1307n ds1307z+t&r 0c to +70c 5.0 8 so (150 mils) tape and reel ds1307 ds1307zn+t&r - 40c to +85c 5.0 8 so (150 mils) tape and reel ds1307n + den otes a lead - free/rohs - compliant package. * a + anywhere on the top mark indicates a lead - free package. an n anywhere on the top mark indicates an industrial temperature range device. underwriters laboratories, inc. is a registered certification mark of underwriters laboratories, inc. ds1307 cpu v cc v cc v cc sda scl gnd x2 x1 v cc r pu r pu crystal sqw/out v bat r pu = t r /c b ds1307 64 x 8, serial, i 2 c real - time clock 1 of 14 rev: 3/15 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock absolute maximum ratings voltage range on any pin relative to ground .................................................................................... - 0.5v to +7.0v operating temperature range (noncondensing) commercial ................................................................................................................................ 0c to +70c industrial .................................................................................................................................. - 40c to +85c storage temperature range ............................................................................................................. - 55c to +125c sol dering temperature (dip, leads) ........................................................................................ +260c for 10 seconds soldering temperature (surface mount)...refer to the jpc/jedec j - std - 020 specification. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ar e stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated i n the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0c to +70c, t a = - 40c to +85c.) (notes 1, 2) parameter symbol conditions min typ max units supply voltage v cc 4.5 5.0 5.5 v logic 1 input v ih 2.2 v cc + 0.3 v logic 0 input v il - 0.3 +0.8 v v bat battery voltage v bat 2.0 3 3.5 v dc electrical characteristics (v cc = 4.5v to 5.5v ; t a = 0c to +70c, t a = - 40c to +85c.) (notes 1, 2) parameter symbol conditions min typ max units input leakage (scl) i li -1 1 a i/o leakage (sda, sqw/out) i lo -1 1 a logic 0 output (i ol = 5ma) v ol 0.4 v active supply current (f scl = 100khz) i cca 1.5 ma standby current i ccs (note 3) 200 a v bat leakage current i batlkg 5 50 na power - fail voltage (v bat = 3.0v) v pf 1.21 6 x v bat 1.25 x v bat 1.284 x v bat v dc electrical characteristics (v cc = 0v, v bat = 3.0v ; t a = 0c to +70c, t a = - 40c to +85c.) (notes 1, 2) parameter symbol conditions min typ max units v bat current (osc on); sqw/out off i bat1 300 500 na v bat cur rent (osc on); sqw/out on (32khz) i bat2 480 800 na v bat data - retention current (oscillator off) i batdr 10 100 na warning: negative undershoots below - 0.3v while the part is in battery - backed mode may cause loss of data. 2 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock ac electrical characteristics (v cc = 4.5v to 5.5v ; t a = 0c to +70c, t a = - 40c to +85c.) parameter symbol conditions min typ max units scl clock frequency f scl 0 100 khz bus free time between a stop and start condition t buf 4.7 s hold time (repeated) start condition t hd:sta (note 4) 4.0 s low period of scl clock t low 4.7 s high period of scl clock t high 4.0 s setup time for a repeated start condition t su:sta 4.7 s data hold time t hd:dat 0 s data setup time t su:dat (notes 5, 6) 250 ns rise time of both sda and scl signals t r 1000 ns fall time of both sda and scl signals t f 300 ns setup time for stop condition t su:sto 4.7 s capacitance (t a = +25c) parameter symbol conditions min typ max units pin capacitance (sda, scl) c i/o 10 pf capacitance load for each bus line c b (note 7) 400 pf note 1: all voltages are referenced to ground. note 2: limits at - 40c are guaranteed by design and are not production tested. note 3: i ccs specified with v cc = 5.0v and sda, scl = 5.0v. note 4: after this period, the first clock pulse is generated. note 5: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 6: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. note 7: c b total capacitance of one bus line in pf. 3 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock timing diagram figure 1 . b lock diagram start sda stop scl t su:sto t hd:sta t su:sta repeated start t hd:dat t high t f t low t r t hd:sta t buf su:dat 4 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock typical operating characteristics (v cc = 5.0v, t a = +25c, unless otherwise noted.) i ccs vs. v cc 0 10 20 30 40 50 60 70 80 90 100 110 120 1.0 2.0 3.0 4.0 5.0 v cc (v) supply current (ua v bat =3.0v i bat vs. temperature 175.0 225.0 275.0 325.0 -40 -20 0 20 40 60 80 temperature (c) supply current (na v cc =0v, v bat =3.0 sqw=32khz sqw of f i bat vs. v bat 100 150 200 250 300 350 400 2.0 2.5 3.0 3.5 v backup (v) supply current (na sqw=32khz sqw of f v cc = 0v sqw/out vs. supply voltage 32768 32768.1 32768.2 32768.3 32768.4 32768.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply (v) frequency (hz) 5 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock pin description pin name function 1 x1 connections for standard 32.768khz quartz crystal. the internal oscillator ci rcuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 12.5pf. x1 is the input to the oscillator and can optionally be connected to an external 32.768khz oscillator. the output of the internal oscillator, x2, is floated if an external oscillator is connected to x1. note: for more information on crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real - time clocks . 2 x2 3 v bat backup supply input for any standard 3v lithium cell or other energy source. battery voltage must be held between the minimum and maximum limits for proper operation. diodes in series between the battery and the v bat pin may prevent proper operation. if a backup supply is not requir ed, v bat must be grounded. the nominal power - fail trip point (v pf ) voltage at which access to the rtc and user ram is denied is set by the internal circuitry as 1.25 x v bat nominal. a lithium battery with 48mah or greater will back up the ds1307 for more than 10 years in the absence of power at +25c. ul recognized to ensure against reverse charging current when used with a lithium battery. go to: www.maxim - ic.com/qa/info/ul/ . 4 gnd ground 5 sda serial data input/output. sda is the data input/output for the i 2 c serial interface. the sda pin is open drain and requires an external pullup resistor. the pullup voltage can be up to 5.5v regardless of the voltage on v cc . 6 scl serial clock input. scl is the clock input for the i 2 c interface and is used to synchronize data movement on the serial interface. the pullup voltage can be up to 5.5v regardless of the voltage on v cc . 7 sqw/out square wave/output driver. when enabled, the sqwe bit set to 1, the sqw/out pin outputs one of four square - wave frequencies (1hz, 4khz, 8khz, 32khz). the sqw/out pin is open drain and requires an external pullup resistor. sqw/out operates with either v cc or v bat applied. the pullup voltage can be up to 5.5v regardless of the voltage on v cc . if not used, this pin can be left floating. 8 v cc primary power supply. when voltage is applied within normal limits, the devi ce is fully accessible and data can be written and read. when a backup supply is connected to the device and v cc is b elow v tp , read and writes are inhibited. however, the timekeeping function continues unaffected by the lower input voltage. detailed description the ds1307 is a low - power clock/calendar with 56 bytes of battery - backed sram. the clock/calendar provides s econds, minutes, hours, day, date, month, and year information. the date at the end of the month is aut omatically adjusted for months with fewer than 31 days, including corrections for leap year . the ds1307 operates as a slave device on the i 2 c bus. access is obtained by implementing a start condition and providing a device identification code followed by a register address. subsequent registers can be accessed sequentially until a stop condition is executed. when v cc falls below 1.25 x v bat , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out - of - tolerance system. when v cc falls below v bat , the device switches into a low - current battery - backup mode. upon power - up, the device switches from battery to v cc when v cc is greater than v bat +0.2v and recognizes inputs when v cc is greater than 1.25 x v bat . the block diagram in figure 1 shows the main elements of the serial rtc. 6 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock oscillator circuit the ds1307 uses an external 32.768khz crystal. the oscillator circuit does not requir e any external resistors or capacitors to operate. table 1 specifies several crystal parameters for the external cryst al. figure 1 shows a functional schematic of the oscillator circuit. if using a crystal w ith the specified characteristics, the startup time is usually less than one second. clock accurac y the accuracy of the clock is dependent upon the accuracy of the crystal and the accur acy of the match between the capacitive load of the oscillator circuit and the capacitive load for which th e crystal was trimmed . additional error will be added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit may result in the clock running fast. refer to application n ote 58: crystal considerations with dallas real - time clocks for detailed information. t able 1 . crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 12.5 pf * the crystal, traces, and crystal input pins should be isolated from rf generating signals. r efer to application note 58: crystal considerations for dallas real - time clocks for additional specifications. figure 2 . recommended layout for crystal rtc and ram address map table 2 shows the address map for the ds1307 rtc and ram registers. the rtc registers are l ocated in address locations 00h to 07h. the ram registers are located in address locations 08h to 3fh. during a multibyte access, when the address pointer reaches 3fh, the end of ram space, it wraps around to location 00h, the beginning of the clock space. note: avoid routing signal lines in the crosshatched area (upper left quadrant) of the package unless there is a ground plane between the signal line and the device package. local ground plan e (layer 2) crystal x1 x2 gnd 7 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock clock and calendar the time and calendar information is obtained by reading the appropriate register b ytes. table 2 shows the rtc r egisters. the time and calendar are set or initialized by writing the appropri ate register bytes. the contents of the time and calendar registers are in the bcd format. the day - of - week register increments at midnight. values that correspond to the day of week are user - defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on.) illogical time and date entries result in undefined operation. bit 7 of register 0 is the c lock halt (ch) bit. when this bit is set to 1, the oscillator is disabled. when cl eared to 0, the oscillator is enabled. on first application of power to the device the time and date registers are typically r eset to 01/01/00 01 00:00:00 (mm/dd/yy dow hh:mm:ss). the ch bit in the seconds register will be set to a 1. the clock can be halted whenever the timekeeping functions are not required, which minimizes current (i batdr ). the ds1307 can be run in either 12 - hour or 24 - hour mode. bit 6 of the hours register is defined as the 12 - hour or 24 - hour mode - select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the second 10 - hour bit (20 to 23 hours). the hours value must be re - entered whenever the 12/24 - hour mode bit is changed . when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to t he internal registers on any i 2 c start. the time information is read from these secondary registers while the clock continues to run. this eliminates the need to re - read the registers in case the internal registers update during a read. the divider chain is reset whenever the seconds register is written. write t ransfers occur on the i 2 c acknowledge from the ds1307. once the divider chain is reset, to avoid rollov er issues, the remaining time and date registers must be written within one second. table 2 . timekeeper registers address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h ch 10 seconds seconds seconds 00 C 59 01h 0 10 minutes minutes minutes 00 C 59 02h 0 12 10 hour 10 hour hours hours 1C 12 +am/pm 00 C 23 24 pm/ am 03h 0 0 0 0 0 day d ay 01 C 07 04h 0 0 10 date date date 01 C 31 05h 0 0 0 10 month month month 01 C 12 06h 10 year year year 00 C 99 07h out 0 0 sqwe 0 0 rs1 rs0 control 08h C 3fh ram 56 x 8 00h C ffh 0 = always reads back as 0. 8 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock control register the ds1307 control register is used to control the operation of the sqw/out pin. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 out 0 0 sqwe 0 0 rs1 rs0 bit 7: output control (out). this bit controls the output level of the sqw/out pin when the square - wave output is disabled. if sqwe = 0, the logic level on the sqw/out pin is 1 if out = 1 and is 0 if out = 0. on initial application of power to the device, this bit is typically set to a 0. bit 4: square - wave enable (sqwe). this bit, when set to logic 1, enables the oscillator output. the frequency of the square - wave output depends upon the value of the rs0 and rs1 bits. with the square - wave output set to 1hz, the clock registers update on the falling edge of the square wave. on initial application of power to the device, this bit i s typically set to a 0. bits 1 and 0: rate select (rs[1:0]). these bits control the frequency of the square - wave output when the square - wave output has been enabled. the following table lists the square - wave frequencies that can be selected with the rs bi ts. on initial application of power to the device, these bits are typically set to a 1. rs1 rs0 sqw/out output sqwe out 0 0 1hz 1 x 0 1 4.096khz 1 x 1 0 8.192khz 1 x 1 1 32.768khz 1 x x x 0 0 0 x x 1 0 1 9 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock i 2 c data bus the ds1307 supports the i 2 c protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. the bus must be controlled b y a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds 1307 operates as a slave on the i 2 c bus. figures 3, 4, and 5 detail how data is transferred on the i 2 c bus. ? data transfer can be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line i s high. changes in the data line while the clock line is high will be interpreted as control signals. accor dingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data tra nsfer: a change in the state of the data line, from low to high, while the clock l ine is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data li ne is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a s top condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte - wise and each receiver acknowledges with a ninth bit. within the i 2 c bus specifications a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defi ned. the ds1307 operates in the standard mode (100khz) only. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which i s associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledg e clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in th is case, the slave must leave the data line high to enable the master to generate the stop condition. 10 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock figure 3 . data transfer on i 2 c serial bus depending upon the state of the r/ w bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each r eceived byte. data is transferred with the most significant bit (msb) first. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. this is followe d by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repe ated start condition is also the beginning of the next serial transfer, the bus will not be released. data is transferred with th e most signifi cant bit (msb) first. acknowledgement signal from receiver acknowledgement signal from receiver r/ w direction bit repeated if more bytes are transfered start condition stop condition or repeated start condition msb 1 2 6 7 8 9 1 2 3-7 8 9 ack ack sda scl 11 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock ... a xxxxxxxx a 1101000 s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start a - acknowledge (ack) p - stop data transferred (x+1 bytes + acknowledge) master to slave slave to master a xxxxxxxx a 1101000 s 1 xxxxxxxx a xxxxxxxx xxxxxxxx a p s - start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge); note: last data byte is followed by a not acknowledge ( a ) signal) master to slave slave to master ... a the ds1307 can operate in the following two modes: 1. slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. hardware performs address recognition after reception of the slave address and direction bit (see figure 4 ). the slave address byte is the first byte rece ived after the master generates the start condition. the slave address byte contains the 7 - bit ds1307 address, which is 1101000, followed by the direction bit (r/ w ), which for a write is 0. after receiving and decoding the slave address byte, the ds1307 outputs an acknowledge on sda. after the ds130 7 acknowledges the slave address + write bit, the master transmits a wor d address to the ds1307. this sets the register pointer on the ds1307, with the ds1307 acknowledging the transfer. the mas ter can then transmit zero or more bytes of data with the ds1307 acknowledging each byte receive d. the register pointer automatically increments after each data byte are written. t he master will generate a stop condition to terminate the data write. 2. slave transmitter mode ( read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the tr ansfer direction is reversed. the ds1307 transmits serial data on sda while the serial clock is input on scl . start and stop conditions are recognized as the beginning and end of a serial transfer (see figure 5 ). the slave address byte is the first byte received after the start condition is generated by the master. the s lave address byte contains the 7 - bit ds1307 address, which is 1101000, followed by the direction bit (r/ w ), which is 1 for a read. after receiving and decoding the slave address the ds1307 outputs an acknowledge on sda. the ds1307 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not writ ten to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the register pointer au tomatically increments after each byte are read. the ds1307 must receive a not acknowledge to end a read. figure 4 . data write slave receiver mode figure 5 . data read slave transmitter mode 12 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock a xxxxxxxx 1101000 s xxxxxxxx a xxxxxxxx xxxxxxxx a p s - start sr - repeated start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge); note: last data byte is followed by a not acknowledge ( a ) signal) master to slave slave to master ... a xxxxxxxx a 0 1101000 sr a 1 a figure 6 . data read (write pointer, then read) slave receive and transmit package information for the latest package outline information and land patterns, go to ww w.maxim - ic.com/packages . package type package code document no. 8 pdip 21 - 0043 8 so 21 - 0041 13 of 14 downloaded from: http:///
ds1307 64 x 8, serial, i 2 c real - time clock revision histo ry revision date description pages changed 100208 moved the typical operating circuit and pin configurations to first page. 1 removed the leaded part numbers from the ordering information table. 1 added an open - drain transistor to sqw/out in the block diagram (figure 1). 4 added the pullup voltage range for sda, scl, and sqw/out to the pin description table and noted that sqw/out can be left open if not used. 6 added default time and date values on first application of power to the clock and calend ar section and deleted the note that initial power - on state is not defined. 8 added default on initial application of power to bit info in the control register section. 9 updated the package information section to reflect new package outline drawing nu mbers. 13 3/15 updated benefits and features section 1 14 of 14 maxim cannot assume responsibility for use of any circuitry other than circuitry entirel y embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2015 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1307ZNTRC02

	To Download DS1307ZNTRC02 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .